1. Field of Invention
The invention relates to a clock and data recovery apparatus and the method thereof, and more particularly to a clock and data recovery apparatus for burst mode clock and data recovery in a passive optical network.
2. Related Art
During the process of data transmission, a transmitter continuous sends digital signals to a receiver. That is, each bit is transmitted within a fixed time. Therefore, the receiver uses a clock and data recovery (CDR) apparatus to generate a clock corresponding to the incoming data, thereby correctly retiming the incoming data. How to make a clock frequency exactly corresponding to a frequency of the incoming data is a very important issue.
As shown in FIG. 1, a conventional clock and data recovery apparatus includes a clock and data recovery circuit 110 and a phase-locked loop (PLL) 120. The PLL 120 generates a system clock Sys CK according to a reference clock Ref CK, and imposes a voltage signal Sv to the clock and data recovery circuit 110. In this case, the clock and data recovery circuit 110 generates a recovered clock CKr with an output frequency corresponding to the voltage signal Sv. The received data DATA are sampled by the recovered clock CKr as data DATAr. This technique has been disclosed in, for example, the U.S. Pat. Nos. 5,237,290 and 6,259,326 B1.
Because of the lack of the feedback control system, the frequency of the conventional CDR may be affected by process variation. Therefore, the output frequency from of CDR is not exactly equal to the data frequency fd, as shown in FIG. 2 (fnom≠fd on the frequency axis). This frequency mismatch will result in a phase shift in each sampling. If the input data are consecutive identical bits, then the phase shifts will accumulate because of the lack of data transitions. In the end, the maximum allowable number of consecutive identical bits to be transmitted has to be restricted. Consequently, the bit error rate (BER) becomes worse when the input stream contains longer consecutive identical bits.